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(parent: 6baa963) | patch
target-arm: implement PD0/PD1 bits for TTBCR
authorFabian Aggeler <aggelerf@ethz.ch>
Thu, 19 Jun 2014 17:06:24 +0000 (18:06 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 19 Jun 2014 17:06:24 +0000 (18:06 +0100)
commite389be1673052b538534643165111725a79e5afd
treefbbc10c005058fbba47a8f5c62e9e5caa48751c7tree
parent6baa963f4dcc211801608ebe1e0482b51653350ccommit | diff
target-arm: implement PD0/PD1 bits for TTBCR

Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).

Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1402409556-18574-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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target-arm/helper.c diff | blob | blame | history
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