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target/arm: Implement REVD
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 8 Jul 2022 15:15:24 +0000 (20:45 +0530)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 11 Jul 2022 12:43:51 +0000 (13:43 +0100)
commit7dbfafc157290b52af6109b82b8398d10ef5c3b3
treee74929c5054c72d53d8cb33df5a338b122d4cc38tree
parent598ab0b24c0cb807b3f380ab422915dd6c229026commit | diff
target/arm: Implement REVD

This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper-sve.h diff | blob | blame | history
target/arm/sve.decode diff | blob | blame | history
target/arm/sve_helper.c diff | blob | blame | history
target/arm/translate-sve.c diff | blob | blame | history
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