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author	Yongbok Kim <yongbok.kim@mips.com>
	Thu, 3 Jan 2019 13:58:16 +0000 (14:58 +0100)
committer	Aleksandar Markovic <amarkovic@wavecomp.com>
	Fri, 18 Jan 2019 15:53:28 +0000 (16:53 +0100)
commit	5fb2dcd17921be71b55fb62d59a12992707d2d3e
tree	ba2673071cd6964bd94d261ff537f0fcc2fdfc20	tree
parent	167db30e981cd72bef15182178037e51afc8e40d	commit \| diff

target/mips: Provide R/W access to SAARI and SAAR CP0 registers

Provide R/W access to SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

target/mips/cpu.h		diff \| blob \| blame \| history
target/mips/helper.h		diff \| blob \| blame \| history
target/mips/internal.h		diff \| blob \| blame \| history
target/mips/op_helper.c		diff \| blob \| blame \| history
target/mips/translate.c		diff \| blob \| blame \| history

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