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target/ppc: Add SPR TBU40
authorSuraj Jitindar Singh <sjitindarsingh@gmail.com>
Thu, 28 Nov 2019 13:46:57 +0000 (14:46 +0100)
committerDavid Gibson <david@gibson.dropbear.id.au>
Mon, 16 Dec 2019 23:39:48 +0000 (10:39 +1100)
commitf0ec31b1e21718b728753bcbfad54862a587050f
tree86855c0dd678f32de9264905b86246ffc7a38087tree
parent32d0f0d8de37519bcaa720c41f0f693b66016f1bcommit | diff
target/ppc: Add SPR TBU40

The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.

This register can only be written by the hypervisor, and cannot be read.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
hw/ppc/ppc.c diff | blob | blame | history
target/ppc/cpu.h diff | blob | blame | history
target/ppc/helper.h diff | blob | blame | history
target/ppc/timebase_helper.c diff | blob | blame | history
target/ppc/translate_init.inc.c diff | blob | blame | history
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