]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/cpu.c
target/riscv: Use official extension names for AIA CSRs
authorAnup Patel <apatel@ventanamicro.com>
Sat, 20 Aug 2022 04:29:58 +0000 (09:59 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 7 Sep 2022 07:18:33 +0000 (09:18 +0200)
commitdc9acc9ce4add37bc5b4437ae9117c318b4f09d4
treed48382a6a930a95a0a1e8860059614eb7828d673
parente0dea2f55f678a1aa1dab3a25c13f52d68b4ec2b
target/riscv: Use official extension names for AIA CSRs

The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).

Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf)

Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
   which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220820042958.377018-1-apatel@ventanamicro.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/riscv_imsic.c
hw/riscv/virt.c
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/csr.c