]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/cpu.h
target/riscv: Add sscofpmf extension support
authorAtish Patra <atishp@rivosinc.com>
Wed, 24 Aug 2022 22:16:57 +0000 (15:16 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 7 Sep 2022 07:19:15 +0000 (09:19 +0200)
commit14664483457b21235be42fbfb534e5ea881508b8
tree760595201df63e91a5d6fc744a953674647c0807
parent3ec0fe18a31fabfe999b480e4c21847ac0d51560
target/riscv: Add sscofpmf extension support

The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension. As the extension doesn't have any
provision for the overflow bit for fixed counters, the fixed events
can also be monitoring using programmable counters. The underlying
counters for cycle and instruction counters are always running. Thus,
a separate timer device is programmed to handle the overflow.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221701.41932-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/csr.c
target/riscv/machine.c
target/riscv/pmu.c
target/riscv/pmu.h