]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/cpu_bits.h
target/riscv: support vector extension csr
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:24:51 +0000 (23:24 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:32 +0000 (09:19 -0700)
commit8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a
treeb7c2700b344ad542b0700e8ecd79479fb2b06f3b
parent32931383270e2ca8209267ca99f23f3c5f780982
target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-4-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h
target/riscv/csr.c