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RISC-V: Implement mstatus.TSR/TW/TVM
authorMichael Clark <mjc@sifive.com>
Mon, 14 Jan 2019 23:58:08 +0000 (23:58 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 11 Feb 2019 23:56:21 +0000 (15:56 -0800)
commit7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3
treeb66e36ce977606f1045348ca8b3b4c0871a64e4dtree
parent533b8f8877d4e3e8bf2b57e633a84afe27c14429commit | diff
RISC-V: Implement mstatus.TSR/TW/TVM

This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Co-authored-by: Matthew Suozzo <msuozzo@google.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/csr.c diff | blob | blame | history
target/riscv/op_helper.c diff | blob | blame | history
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