]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/csr.c
target/riscv: Implement hgeie and hgeip CSRs
authorAnup Patel <anup.patel@wdc.com>
Fri, 4 Feb 2022 17:46:39 +0000 (23:16 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:18 +0000 (12:24 +1000)
commitcd032fe75c1f7b24ccad772d50bfb689e7f5835d
treea7b62cfd8789ad2fae5409c76d32453cc1cbcac0
parent881df35d3df52efd845087fb76d0b0116b366468
target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c
target/riscv/csr.c
target/riscv/machine.c