]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/csr.c
target/riscv: Implement AIA interrupt filtering CSRs
authorAnup Patel <anup.patel@wdc.com>
Fri, 4 Feb 2022 17:46:48 +0000 (23:16 +0530)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:19 +0000 (12:24 +1000)
commitd0237b4df07e7b532b9b917639d6eb6b2c825c67
tree95c7b6e25792c4df7554b2c13951b5841cfa2670
parent2b6023987955a887aae3ad6882557960b2253a4f
target/riscv: Implement AIA interrupt filtering CSRs

The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.

At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/csr.c