]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/insn32.decode
target/riscv: add vector configure instruction
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:24:52 +0000 (23:24 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:32 +0000 (09:19 -0700)
commit2b7168fc43fb270fb89e1dddc17ef54714712f3a
tree16f1ef7e07de0c8454d93c3cd28536a8d92247f0
parent8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a
target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/Makefile.objs
target/riscv/cpu.h
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvv.inc.c [new file with mode: 0644]
target/riscv/translate.c
target/riscv/vector_helper.c [new file with mode: 0644]