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(parent: d71a24f) | patch
target/riscv: rvv-1.0: set-X-first mask bit instructions
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:17 +0000 (15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (14:51 +1000)
commit40c1495d69b17d34f073a5b92970b1b82e6ad7ef
treef40f03a77c2cd519321b6965969b289a4f18b2b6tree
parentd71a24fc82c50f6fe0d86feece01a4ef43b1af82commit | diff
target/riscv: rvv-1.0: set-X-first mask bit instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-32-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn32.decode diff | blob | blame | history
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
target/riscv/vector_helper.c diff | blob | blame | history
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