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target/riscv: rvv-1.0: register gather instructions
authorFrank Chang <frank.chang@sifive.com>
Fri, 10 Dec 2021 07:56:21 +0000 (15:56 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (14:51 +1000)
commit50bfb45b2c5bbbac8ffb7f051eb8c88128cae88d
tree7a6f022d995276751fc6953c80800bc93f21033ftree
parent308ee805786a18f236daead36b11f53cd5017899commit | diff
target/riscv: rvv-1.0: register gather instructions

* Add vrgatherei16.vv instruction.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-36-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h diff | blob | blame | history
target/riscv/insn32.decode diff | blob | blame | history
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
target/riscv/vector_helper.c diff | blob | blame | history
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