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(parent: d384292) | patch
target/riscv: vector single-width bit shift instructions
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:25:02 +0000 (23:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commit3277d955d21d8943d80062b4cfd8547f831dbd51
treede4545ef16b3d93d0638c8224d1b8ae11a80c545tree
parentd3842924cf93d104f691c5ea9090d6700ccef281commit | diff
target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-15-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h diff | blob | blame | history
target/riscv/insn32.decode diff | blob | blame | history
target/riscv/insn_trans/trans_rvv.inc.c diff | blob | blame | history
target/riscv/vector_helper.c diff | blob | blame | history
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