]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/insn_trans/trans_rvv.inc.c
target/riscv: vector single-width integer add and subtract
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:24:58 +0000 (23:24 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commit43740e3a3b3bb66456103684e622ba4e9baae297
treeb8b40bdfdd022b437b0745e86fad96bd0d3e5d62
parent268fcca66bde62257960ec8d859de374315a5e3d
target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvv.inc.c
target/riscv/vector_helper.c