]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/insn_trans/trans_rvv.inc.c
target/riscv: vector wideing integer reduction instructions
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:25:34 +0000 (23:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commitbba718200b2d2aac6ab5031817f7125571c983a1
treef123d23a0c4cfa5c4e0111058a28834f32471b59
parentfe5c9ab1fc185e96bf7e034954127429ca74d386
target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-47-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvv.inc.c
target/riscv/vector_helper.c