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]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/insn_trans/trans_rvv.inc.c

author	LIU Zhiwei <zhiwei_liu@c-sky.com>
	Wed, 1 Jul 2020 15:25:37 +0000 (23:25 +0800)
committer	Alistair Francis <alistair.francis@wdc.com>
	Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commit	c21f34aebfb15c112131e36f425986170a3fcae9
tree	e69536ab662cc374a6ad9dc6bc8ba92cc2d43257	tree
parent	696b0c260a0312c865cd0e4a8f09d0b9f13b07c9	commit \| diff

target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

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target/riscv/helper.h		diff \| blob \| blame \| history
target/riscv/insn32.decode		diff \| blob \| blame \| history
target/riscv/insn_trans/trans_rvv.inc.c		diff \| blob \| blame \| history
target/riscv/vector_helper.c		diff \| blob \| blame \| history