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(parent: ec17e03) | patch
target/riscv: vector register gather instruction
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Wed, 1 Jul 2020 15:25:47 +0000 (23:25 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 2 Jul 2020 16:19:33 +0000 (09:19 -0700)
commite4b83d5c0928507cc27a0f613675b117db9993e4
tree9ec69c69412bd7cb4a862ca5f608868e652eb053tree
parentec17e03688ce4d0ae188db6d90b185b92a9a2087commit | diff
target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-60-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/helper.h diff | blob | blame | history
target/riscv/insn32.decode diff | blob | blame | history
target/riscv/insn_trans/trans_rvv.inc.c diff | blob | blame | history
target/riscv/vector_helper.c diff | blob | blame | history
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