]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/insn_trans/trans_xthead.c.inc
RISC-V: Adding XTheadCmo ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Tue, 31 Jan 2023 20:20:00 +0000 (21:20 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 6 Feb 2023 22:19:23 +0000 (08:19 +1000)
commit49a7f3aabba99e06768cbaf6c9429f514a9c7444
tree71833d4e2e94ef9820a50b6cd8c9bf0a4bd54a72
parent4b402886ac89732f903094004612039d0fd5b4cb
RISC-V: Adding XTheadCmo ISA extension

This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.

The implementation does not have much functionality (besides accepting
the instructions and not qualifying them as illegal instructions if
the hart executes in the required privilege level for the instruction),
as QEMU does not model CPU caches and instructions are documented
to not raise any exceptions.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn_trans/trans_xthead.c.inc [new file with mode: 0644]
target/riscv/meson.build
target/riscv/translate.c
target/riscv/xthead.decode [new file with mode: 0644]