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(parent: 4b37aaa) | patch
target/xtensa: implement MEMCTL SR
authorMax Filippov <jcmvbkbc@gmail.com>
Sat, 12 Nov 2016 06:40:18 +0000 (22:40 -0800)
committerMax Filippov <jcmvbkbc@gmail.com>
Sun, 15 Jan 2017 21:01:56 +0000 (13:01 -0800)
commit9e03ade4411c81a7f7d974dcedf0390835ce4096
tree5ed7163044ac610d041277e20def7990e507b1b5tree
parent4b37aaa879d508494df14bdc49830cdf8aa77a57commit | diff
target/xtensa: implement MEMCTL SR

MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target/xtensa/cpu.c diff | blob | blame | history
target/xtensa/cpu.h diff | blob | blame | history
target/xtensa/helper.h diff | blob | blame | history
target/xtensa/op_helper.c diff | blob | blame | history
target/xtensa/overlay_tool.h diff | blob | blame | history
target/xtensa/translate.c diff | blob | blame | history
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