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target-xtensa: implement RER/WER instructions
authorMax Filippov <jcmvbkbc@gmail.com>
Sat, 26 Nov 2011 11:48:41 +0000 (15:48 +0400)
committerMax Filippov <jcmvbkbc@gmail.com>
Tue, 17 Jan 2017 03:19:03 +0000 (19:19 -0800)
commit3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02
treed64a088bd5188f6b19fe1fcd341283140f5fcc0etree
parent8b912ff033cbc2e58476dfdc00fa2b8529c9eb96commit | diff
target-xtensa: implement RER/WER instructions

RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target/xtensa/cpu.c diff | blob | blame | history
target/xtensa/cpu.h diff | blob | blame | history
target/xtensa/helper.h diff | blob | blame | history
target/xtensa/op_helper.c diff | blob | blame | history
target/xtensa/overlay_tool.h diff | blob | blame | history
target/xtensa/translate.c diff | blob | blame | history
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