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(parent: 3940433) | patch
target-arm: Add support for A32 and T32 HVC and SMC insns
authorPeter Maydell <peter.maydell@linaro.org>
Fri, 24 Oct 2014 11:19:13 +0000 (12:19 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 24 Oct 2014 11:19:13 +0000 (12:19 +0100)
commit37e6456ef539b2c4d1b9438f3df90eb032a9618f
treed7bc890b4fb05b19f12223ba63bad55005565ee6tree
parent394043384337d3e84fe92ecc83bd90b0dcd661d5commit | diff
target-arm: Add support for A32 and T32 HVC and SMC insns

Add support for HVC and SMC instructions to the A32 and
T32 decoder. Using these for real exceptions to EL2 or EL3
is currently not supported (the do_interrupt routine does
not handle them) but we require the instruction support to
implement PSCI.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1412865028-17725-6-git-send-email-peter.maydell@linaro.org
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target-arm/translate.c diff | blob | blame | history
target-arm/translate.h diff | blob | blame | history
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