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author	ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
	Sun, 28 Oct 2007 19:45:05 +0000 (19:45 +0000)
committer	ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
	Sun, 28 Oct 2007 19:45:05 +0000 (19:45 +0000)
commit	623a930ec30a75e6d6482ca8208d7bf1ca8d359b
tree	6953605abd679c357ffba546fd43907a4ce9ea0e	tree
parent	8e129e0748f866d730f1e39bff296219fedac244	commit \| diff

Implement missing MIPS supervisor mode bits.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162

cpu-defs.h		diff \| blob \| blame \| history
linux-user/elfload.c		diff \| blob \| blame \| history
target-mips/cpu.h		diff \| blob \| blame \| history
target-mips/exec.h		diff \| blob \| blame \| history
target-mips/helper.c		diff \| blob \| blame \| history
target-mips/op.c		diff \| blob \| blame \| history
target-mips/op_helper.c		diff \| blob \| blame \| history
target-mips/translate.c		diff \| blob \| blame \| history

Qemu copy for testing