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author	Yongbok Kim <yongbok.kim@mips.com>
	Thu, 3 Jan 2019 15:46:32 +0000 (16:46 +0100)
committer	Aleksandar Markovic <amarkovic@wavecomp.com>
	Fri, 18 Jan 2019 15:53:28 +0000 (16:53 +0100)
commit	043715d1e0fbb3e3411be3f898c5b77b7f90327a
tree	1e92367ebcd199a0e18f4b4233e076299946c440	tree
parent	e5345d96752a9dec441b022502be34e01bcacca8	commit \| diff

target/mips: Update ITU to utilize SAARI and SAAR CP0 registers

Update ITU to utilize SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

hw/mips/cps.c		diff \| blob \| blame \| history
hw/misc/mips_itu.c		diff \| blob \| blame \| history
include/hw/misc/mips_itu.h		diff \| blob \| blame \| history
target/mips/cpu.h		diff \| blob \| blame \| history
target/mips/op_helper.c		diff \| blob \| blame \| history

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