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drm/i915/dg1: Add DPLL macros for DG1
authorAditya Swarup <aditya.swarup@intel.com>
Wed, 14 Oct 2020 19:19:30 +0000 (12:19 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Thu, 15 Oct 2020 21:14:30 +0000 (14:14 -0700)
commit049c651b6d93839c74be5cb24708f1d8470ec60d
tree5a2d1f649f44a710d5378eef4508f55425dc8ce8tree
parent240abb3c76ff4b469f91a753adb8426b77cab914commit | diff
drm/i915/dg1: Add DPLL macros for DG1

DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2.

Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.

Bspec: 50288, 50299

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-4-lucas.demarchi@intel.com
drivers/gpu/drm/i915/display/intel_dpll_mgr.h diff | blob | blame | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
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