drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver

drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver

BugLink: https://launchpad.net/bugs/1811200
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
counters. All counters lack overflow interrupt and are
sampled periodically.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
[will: consistent enum cpuhp_state naming]
Signed-off-by: Will Deacon <will.deacon@arm.com>
(backported from commit 69c32972d59388c041268e8206e8eb1acff29b9a)
Signed-off-by: Ike Panhc <ike.pan@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>