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(parent: 93c9c19) | patch
drm/i915: Replace hardcoded cacheline size with macro
authorChris Wilson <chris@chris-wilson.co.uk>
Wed, 9 Apr 2014 08:19:40 +0000 (09:19 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 5 May 2014 07:08:36 +0000 (09:08 +0200)
commit18393f6322ce523efa767e7ed9bd64fe0645e458
treee7b6975c25580d25a3729c04218826f0feb96457tree
parent93c9c19b3d259a76fc2efa4b8f2478dc9f339beecommit | diff
drm/i915: Replace hardcoded cacheline size with macro

For readibility and guess at the meaning behind the constants.

v2: Claim only the meagerest connections with reality.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | blame | history
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