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(parent: 7f1b17f) | patch
Implement address masking for SPARC v9 CPUs
authorArtyom Tarasenko <atar4qemu@gmail.com>
Sat, 12 May 2012 09:15:20 +0000 (11:15 +0200)
committerBlue Swirl <blauwirbel@gmail.com>
Sat, 12 May 2012 09:46:00 +0000 (09:46 +0000)
commit22036a49dd618051d932177b5d93daee746e5609
tree6c41c7396127cbbe7e57ef89a15079c1513d2b3ctree
parent7f1b17f2974ba0981e12615129e56b92ce31afa4commit | diff
Implement address masking for SPARC v9 CPUs

According to UltraSPARC - IIi User's manual:

14.1.11 Address Masking (Impdep #125)
When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
transmit zero in the high-order 32-bits of the PC to their specified
destination registers.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc/translate.c diff | blob | blame | history
Qemu copy for testing