]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
authorWeiwei Li <liweiwei@iscas.ac.cn>
Thu, 30 Mar 2023 03:46:36 +0000 (11:46 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 5 May 2023 00:49:50 +0000 (10:49 +1000)
commit22c2f87ab2e5c2a57e4a2ab2a02e89fe4dad608a
tree2b05482abc46d398599705459b4108f64aeca706
parent77dff6509c5655fe959acf7a6d4fe923b6f292b8
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvh.c.inc