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disas/riscv Fix ctzw disassemble
authorIvan Klokov <ivan.klokov@syntacore.com>
Fri, 17 Feb 2023 15:14:59 +0000 (18:14 +0300)
committerPalmer Dabbelt <palmer@rivosinc.com>
Sun, 5 Mar 2023 20:43:38 +0000 (12:43 -0800)
commit270629024df1f9f4e704ce8325f958858c5cbff7
tree55a7ed05e9b5aced1ebfa263a0bb247ab0ab6d0ftree
parent007698632814b4b4aeae1a9c176d932951e9c8cfcommit | diff
disas/riscv Fix ctzw disassemble

Due to typo in opcode list, ctzw is disassembled as clzw instruction.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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