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clk: xgene: Fix divider with non-zero shift value
authorLoc Ho <lho@apm.com>
Thu, 19 Nov 2015 19:20:30 +0000 (12:20 -0700)
committerTim Gardner <tim.gardner@canonical.com>
Mon, 29 Feb 2016 15:57:17 +0000 (08:57 -0700)
commit4114fd770891d1ec0c3e6c6b37bbafdfc0fa4c47
treea74d2409c8f15a3267d956cfbb74cb3763863a12tree
parent07ceaa64d24b7bd95f5ecdc8361b0df4eb0405cdcommit | diff
clk: xgene: Fix divider with non-zero shift value

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit 1382ea631ddddb634850a3795527db0feeff5aaf)
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
drivers/clk/clk-xgene.c diff | blob | blame | history
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