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KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch
authorRadim Krčmář <rkrcmar@redhat.com>
Fri, 6 Oct 2017 17:25:55 +0000 (19:25 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 12 Oct 2017 12:01:54 +0000 (14:01 +0200)
commit44275932589a84a24849290b0d5c22157016a5e6
tree057272d4093341735845152b4da89d5b05a76bbdtree
parent5d74a6999368ad1991491b1913bb80faf1925e67commit | diff
KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

Our routines look at tscdeadline and period when deciding state of a
timer.  The timer is disarmed when switching between TSC deadline and
other modes, so we should set everything to disarmed state.

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/lapic.c diff | blob | blame | history
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