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target/mips: Enable LBX/LWX/* instructions for Octeon
authorPavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Tue, 1 Nov 2022 05:29:44 +0000 (08:29 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Tue, 8 Nov 2022 00:04:25 +0000 (01:04 +0100)
commit4525ea7e0caa4aa6317204cd977179dea972cf6d
tree7f8973dd706a751a9b138a7fc8cb77317da09648tree
parent0e8b3010afa7507f42754ebec16bbd4dfdb3a660commit | diff
target/mips: Enable LBX/LWX/* instructions for Octeon

This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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