]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: Add checks for several RVC reserved operands
authorRichard Henderson <richard.henderson@linaro.org>
Thu, 25 Apr 2019 17:26:36 +0000 (10:26 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 24 May 2019 19:09:25 +0000 (12:09 -0700)
commit4cc16b3b9282e04fab8e84d136540757e82af019
treea6caaae619e90e0d1bd36105f1fb986847435c53
parente06431108b0b1ef6ca76398d2b0b792ea24ae6bc
target/riscv: Add checks for several RVC reserved operands

C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/insn16-64.decode
target/riscv/insn16.decode