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drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT
authorChangbin Du <changbin.du@intel.com>
Tue, 15 May 2018 02:35:35 +0000 (10:35 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Mon, 9 Jul 2018 02:22:50 +0000 (10:22 +0800)
commit52ca14e6844a04e174b5cd3d7dbf63a23271775c
tree5d21f64cc6f50afc3c4910b573d87d3120aeb0d2tree
parent6fd7937832698e73a5719ff488c2fc5e22c9c0bacommit | diff
drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT

The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA
from GEN8 which can control IPS enabling.

v3: MMIO control for IPS is not removed from gen9 but gen10 (Matthew Auld)
v2: IPS of all engines must be enabled together for gen9.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/handlers.c diff | blob | blame | history
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