]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/commit
powerpc/mm: Fixup tlbie vs store ordering issue on POWER9
authorAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Fri, 23 Mar 2018 04:56:27 +0000 (10:26 +0530)
committerSeth Forshee <seth.forshee@canonical.com>
Tue, 3 Apr 2018 18:55:51 +0000 (13:55 -0500)
commit543ef34ff3cb0b6079fdbe24a66746b3e35aae45
tree3206b082fff931df44d610cd87fc21c4598937da
parent63887dabf7e81c4b999430c8f1e7b39fb707570b
powerpc/mm: Fixup tlbie vs store ordering issue on POWER9

BugLink: http://bugs.launchpad.net/bugs/1758910
On POWER9, under some circumstances, a broadcast TLB invalidation
might complete before all previous stores have drained, potentially
allowing stale stores from becoming visible after the invalidation.
This works around it by doubling up those TLB invalidations which was
verified by HW to be sufficient to close the risk window.

This will be documented in a yet-to-be-published errata.

Fixes: 1a472c9dba6b ("powerpc/mm/radix: Add tlbflush routines")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[mpe: Enable the feature in the DT CPU features code for all Power9,
      rename the feature to CPU_FTR_P9_TLBIE_BUG per benh.]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(backported from a5d4b5891c2f1f865a2def1eb0030f534e77ff86 linux-next)
Signed-off-by: Gustavo Walbon <gwalbon@linux.vnet.ibm.com>
Signed-off-by: Seth Forshee <seth.forshee@canonical.com>
arch/powerpc/include/asm/cputable.h
arch/powerpc/kernel/dt_cpu_ftrs.c
arch/powerpc/kvm/book3s_64_mmu_radix.c
arch/powerpc/kvm/book3s_hv_rm_mmu.c
arch/powerpc/mm/hash_native_64.c
arch/powerpc/mm/pgtable_64.c
arch/powerpc/mm/tlb-radix.c