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clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
authorDinh Nguyen <dinguyen@kernel.org>
Tue, 16 Jun 2020 20:24:16 +0000 (15:24 -0500)
committerStephen Boyd <sboyd@kernel.org>
Sat, 20 Jun 2020 02:27:33 +0000 (19:27 -0700)
commit6f3bcf56f8eec78e51cac8b3dd67ed7ec67e3e1e
tree7e02a1d5cc0ae6366ef68bbc4c75d8f0d2d14842tree
parentc2710fdf935bb1286e8eb6a6b44991bab1fe87afcommit | diff
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk

And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/socfpga/clk-agilex.c diff | blob | blame | history
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