]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commit
MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier
authorFlorian Fainelli <f.fainelli@gmail.com>
Mon, 4 Apr 2016 17:55:35 +0000 (10:55 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 13 May 2016 12:02:06 +0000 (14:02 +0200)
commit73c4ca047f440c79f545bc6133e3033f754cd239
tree340a527a9d89d805b07b7f1a6113c53d13f041ed
parentc130d2fd3d59fbd5d269f7d5827bd4ed1d94aec6
MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier

BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is
properly handled by the per-CPU override added at the end of
r4k_cache_init(), the problem is that the output of probe_pcache()
disagrees with that, since this is too late:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes

With the change moved earlier, we now have a consistent output with the
settings we are intending to have:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13011/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c