]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commit
drm/i915: Move vlv_init_display_clock_gating() to the display power well
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 11 Apr 2016 13:56:30 +0000 (16:56 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 12 Apr 2016 16:09:07 +0000 (19:09 +0300)
commit766078df43db7227e6904bb51de636a4abedb01b
tree73ba55cdbddc06b7288976db5a03a944c0c31bc2
parent6b7eafc1b43d584081bfa6e8bd758121de18ca04
drm/i915: Move vlv_init_display_clock_gating() to the display power well

The registers frobbed by vlv_init_display_clock_gating() libve inside
the disp2d power well, so frobbing them while the power well is down
results in unclaimed register access warning (and of course the values
won't stick). Let's do this setup after we know the power well is
enabled.

It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their state
when the power well goes down, but fortunately the values we've been
writing are actually the reset defaults.

MI_ARB_VLV actually retains its value even if the power well was turned
off, we just can't access it while the power well is down.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460382992-28728-9-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_runtime_pm.c