]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: modification of the trans_csrxx for 128-bit support
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Thu, 6 Jan 2022 21:01:07 +0000 (22:01 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:10 +0000 (15:46 +1000)
commit7934fdeee75c8d8ca02a396afc549e3f54303859
treef033a5e34b92d44e096b99852495ab960e3c1c24
parent961738ffea964daad464389b3f06dd5b245fdf3c
target/riscv: modification of the trans_csrxx for 128-bit support

As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvi.c.inc