]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: support for 128-bit arithmetic instructions
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Thu, 6 Jan 2022 21:01:03 +0000 (22:01 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 8 Jan 2022 05:46:10 +0000 (15:46 +1000)
commit7fd40f8679ceed388d82902e9be05ae136cf09cd
tree5ed56b39753aa3b762b671ac373d96ab587a4f0a
parent6bf4bbed205127f3805e960a1213c2289db89114
target/riscv: support for 128-bit arithmetic instructions

Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvb.c.inc
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/insn_trans/trans_rvm.c.inc
target/riscv/translate.c