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(parent: 2585cf9) | patch
powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR
authorZhang Rui <rui.zhang@intel.com>
Tue, 7 Dec 2021 13:17:34 +0000 (21:17 +0800)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Fri, 17 Dec 2021 15:13:14 +0000 (16:13 +0100)
commit931da6a0de5d620425af4425344259e6ff46b654
tree1be032747e0198dfd3b7652b554b8f93313e0062tree
parent2585cf9dfaaddf00b069673f27bb3f8530e2039ccommit | diff
powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR

On Sapphire Rapids, the layout of the Psys domain Power Limit Register
is different from from what it was before.

Enhance the code to support the new Psys PL register layout.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reported-and-tested-by: Alkattan Dana <dana.alkattan@intel.com>
[ rjw: Subject and changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
drivers/powercap/intel_rapl_common.c diff | blob | blame | history
include/linux/intel_rapl.h diff | blob | blame | history
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