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ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Sat, 23 Jan 2016 08:55:30 +0000 (17:55 +0900)
committerThierry Reding <treding@nvidia.com>
Tue, 12 Apr 2016 15:09:28 +0000 (17:09 +0200)
commit955d809bdeaea3663cf6ac1ee72cd50775bbab9d
tree8cc239724e40264746c379065f322ffa7a50d482tree
parentf55532a0c0b8bb6148f4e07853b876ef73bc69cacommit | diff
ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select

These two are both ARMv7 SoCs.  They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.

Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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