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powerpc/selftests: Check endianness on trap in TM
authorGustavo Romero <gromero@linux.vnet.ibm.com>
Sun, 31 Dec 2017 23:20:46 +0000 (18:20 -0500)
committerMichael Ellerman <mpe@ellerman.id.au>
Sun, 21 Jan 2018 18:48:37 +0000 (05:48 +1100)
commita08082f8e4e1c292df174a9ed303cfbff2fbe2cb
tree78e3001d940ce055f67fa379f9bac9f05a212e86tree
parent1c200e63d055ec0125e44a5e386b9b78aada7eb3commit | diff
powerpc/selftests: Check endianness on trap in TM

Add a selftest to check if endianness is flipped inadvertently to BE
(MSR.LE set to zero) on BE and LE machines when a trap is caught in
transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP
and MSR.VEC are zeroed (disabled).

Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
tools/testing/selftests/powerpc/tm/.gitignore diff | blob | blame | history
tools/testing/selftests/powerpc/tm/Makefile diff | blob | blame | history
tools/testing/selftests/powerpc/tm/tm-trap.c [new file with mode: 0644] blob
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