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(parent: d75c135) | patch
target-mips: generate a reserved instruction exception on CPU without DSP
authorAurelien Jarno <aurelien@aurel32.net>
Tue, 1 Jan 2013 17:02:23 +0000 (18:02 +0100)
committerAurelien Jarno <aurelien@aurel32.net>
Thu, 31 Jan 2013 22:29:36 +0000 (23:29 +0100)
commitad153f153da08f5e08bc8e433c0070af53e34e0a
treeed063d1f4b6903aeb2ac7961392fb3e138626331tree
parentd75c135e6b6255787dfc01ce997862d820ed1d36commit | diff
target-mips: generate a reserved instruction exception on CPU without DSP

On CPU without DSP ASE support, a reserved instruction exception (instead of
a DSP ASE sate disabled) should be generated.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips/translate.c diff | blob | blame | history
Qemu copy for testing