Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next
* clk-mediatek:
clk: mediatek: add audsys support for MT2701
clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
dt-bindings: clock: mediatek: add audsys support for MT2701
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
clk: mediatek: update missing clock data for MT7622 audsys
clk: mediatek: fix PWM clock source by adding a fixed-factor clock
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
* clk-hisi:
clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
clk: hisilicon: mark wdt_mux_p[] as const
clk: hisilicon: Mark phase_ops static
clk: hi3798cv200: add emmc sample and drive clock
clk: hisilicon: add hisi phase clock support
clk: hi3798cv200: add COMBPHY0 clock support
clk: hi3798cv200: fix define indentation
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
clk: hi3798cv200: correct IR clock parent
clk: hi3798cv200: fix unregister call sequence in error path
* clk-allwinner:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name