Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging

Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging

Fourth RISC-V PR for QEMU 7.1

* Update MAINTAINERS
* Add support for Zmmul extension
* Fixup FDT errors when supplying device tree from the command line for virt machine
* Avoid overflowing the addr_config buffer in the SiFive PLIC
* Support -device loader addresses above 2GB
* Correctly wake from WFI on VS-level external interrupts
* Fixes for RV128 support
* Support Vector extension tail agnostic setting elements' bits to all 1s
* Don't expose the CPU properties on named CPUs
* Fix vector extension assert for RV32

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* tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu: (25 commits)
  target/riscv: trans_rvv: Avoid assert for RV32 and e64
  target/riscv: Don't expose the CPU properties on names CPUs
  target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
  target/riscv: rvv: Add tail agnostic for vector permutation instructions
  target/riscv: rvv: Add tail agnostic for vector mask instructions
  target/riscv: rvv: Add tail agnostic for vector reduction instructions
  target/riscv: rvv: Add tail agnostic for vector floating-point instructions
  target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
  target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
  target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
  target/riscv: rvv: Add tail agnostic for vector integer shift instructions
  target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
  target/riscv: rvv: Add tail agnostic for vector load / store instructions
  target/riscv: rvv: Add tail agnostic for vv instructions
  target/riscv: rvv: Early exit when vstart >= vl
  target/riscv: rvv: Rename ambiguous esz
  target/riscv: rvv: Prune redundant access_type parameter passed
  target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
  target/riscv/debug.c: keep experimental rv128 support working
  target/riscv: Wake on VS-level external interrupts
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>