]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 18 May 2022 01:26:11 +0000 (09:26 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 24 May 2022 00:38:50 +0000 (10:38 +1000)
commitbb06941f95edd8a231bee0ac52a8a1dbf6b08e6a
treeec2589c6948061dd7f9ff548e9fdae241dbd2e21
parent96c7fff703d56798bd5dcb1ef6d42ead144580a3
target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

 - setting ext_g will implicitly set ext_i

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c