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KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
authorSean Christopherson <sean.j.christopherson@intel.com>
Tue, 3 Mar 2020 02:02:36 +0000 (18:02 -0800)
committerPaolo Bonzini <pbonzini@redhat.com>
Mon, 16 Mar 2020 16:57:44 +0000 (17:57 +0100)
commitbb1fcc70d98f040e3cc469b079d3f38fc541cb95
tree318393d7e8b0fda9862851dc9207f6c89def3b75tree
parent8053f924cad30bf9f9a24e02b6c8ddfabf5202eacommit | diff
KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT

Add support for 5-level nested EPT, and advertise said support in the
EPT capabilities MSR.  KVM's MMU can already handle 5-level legacy page
tables, there's no reason to force an L1 VMM to use shadow paging if it
wants to employ 5-level page tables.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/include/asm/vmx.h diff | blob | blame | history
arch/x86/kvm/mmu/mmu.c diff | blob | blame | history
arch/x86/kvm/mmu/paging_tmpl.h diff | blob | blame | history
arch/x86/kvm/vmx/nested.c diff | blob | blame | history
arch/x86/kvm/vmx/vmx.c diff | blob | blame | history
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