]> git.proxmox.com Git - mirror_qemu.git/commit
hw/cxl: Fix missing reserved data in CXL Device DVSEC
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Fri, 8 Mar 2024 14:38:31 +0000 (14:38 +0000)
committerMichael S. Tsirkin <mst@redhat.com>
Tue, 12 Mar 2024 21:59:48 +0000 (17:59 -0400)
commitbfc2f7a6caa6843e50019ee2511ad11cd5582711
treef58274f157f06411c9f2ba4a2b144f6c7efa743d
parent74e2845c5f95b0c139c79233ddb65bb17f2dd679
hw/cxl: Fix missing reserved data in CXL Device DVSEC

The r3.1 specification introduced a new 2 byte field, but
to maintain DWORD alignment, a additional 2 reserved bytes
were added. Forgot those in updating the structure definition
but did include them in the size define leading to a buffer
overrun.

Also use the define so that we don't duplicate the value.

Fixes: Coverity ID 1534095 buffer overrun
Fixes: 8700ee15de ("hw/cxl: Standardize all references on CXL r3.1 and minor updates")
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240308143831.6256-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
include/hw/cxl/cxl_pci.h